Detection and Avoidance of Counterfeit ICs and Components

Counterfeit electronics in the supply chain are a longstanding problem with nontrivial impacts to government, industry, and society as a whole: (i) they create security and reliability risks for the life-critical systems and infrastructures that incorporate them since they have far lower reliability than the parts they are meant to mimic; (ii) they result in substantial economic losses for Intellectual Property (IP) owners; (iii) their sale is a source of revenue for various groups that threaten the safety and integrity of modern society, such as terrorist groups and organized crime; (iv) their existence reduces the incentive to develop new products and ideas, thereby impacting worldwide innovation, economic growth, and employment. Further, recent data from the Government and Industry Data Exchange Program (GIDEP) and Information Handling Services (IHS) indicate that counterfeit electronics are still on the rise. Thus, there has become increasing interest in detecting and avoiding counterfeit components before they can do damage.

Counterfeit detection of electronic parts can be classified into two main categories: physical inspection and electrical testing. The physical inspection techniques examine the IC or component package exterior and interior, and range from simple visual inspection to high-tech imaging solutions that require X-ray, Infrared, transmission electron microscopy (TEMs), focused ion beams (FIBs), etc. The electrical tests capture chip curve trace, contact degradation, device parameter distributions, etc. and compare them to the device specifications. Both approaches come with their own advantages and disadvantages. Physical inspection more easily extends to different integrated circuit (IC) and electronic component types. However, physical inspection still suffers from some significant challenges including: (i) low confidence and large overheads associated with the tests/equipment specified required by test standards; (ii) destructive nature of some techniques; (iii) lack of understanding of what defects are associated with each counterfeit type; (iv) little if any metrics, data, etc. to facilitate automation in testing and classification of counterfeit components. Electrical tests suffer from various challenges as well including (i) they demand knowledge and required a particular test-setup for each integrated circuit (IC) and/or component type; (ii) they must distinguish between performance degradation due to counterfeiting and due to unavoidable process variations.

In our work, we have investigated the current state of supply chain and developed various approaches to overcome the limitations of prior work:

  1. Counterfeit IC Repository:One of the most significant barriers to overcoming the above challenges is a lack of data, especially with respect to physical inspection. Developing and improving counterfeit detection through physical inspection requires images and measurements from a variety of counterfeit ICs. In general, researchers in academia do not have access to the state-of-the-art equipment, counterfeit samples, and experience necessary to perform physical inspection on suspect parts. On the other hand, the test labs with access do not have the time, resources, and motivation to devote to exhaustive data collection. As part of our NSF projects, we have developed the first counterfeit IC repository (counterfeit-ic.org) with the primary goal of providing the community with access to such data. Using the equipment in our world-class lab, we have extracted images of defects from hundreds of chips, computed statistical information about defects, and uploaded all data to the repository. We have also provided templates that allows others to share their own data on the repository.
  2. Design-for-Anti-Counterfeit (DfAC):There are seven types of counterfeits in the supply chain – recycled, remarked, overproduced, out-of-spec/defective, cloned, forged documentation, and tampered. Existing approaches for physical inspection are geared mostly towards detection of recycled and remarked parts. Parts that are currently being designed could benefit from effective, low-cost avoidance mechanisms which could (i) avoid the need to apply physical inspection; (ii) aid in detection of certain counterfeit types; (iii) prevent or hinder an attackers capability to successfully overproduce, clone, or tamper with a component. We refer to these as Design-for-Anti-Counterfeit (DfAC) techniques. Our work includes sensors that detect recycling of large and small digital ICs, small analog components, etc. We have also developed secure test protocols that hinder defective part sourcing, overproduction, and cloning of digital ICs. To protect low-volume electronic chips, such as those designed for critical systems, we developed the first chip-edit based obfuscation approaches. Finally, we have proposed and demonstrated several RFID-based solutions that provide electronic system trace-and-trace and provenance capabilities for supply chains.
  3. Advanced Physical Inspection and Electrical Tests: We have investigated several ways to improve the effectiveness and efficiency of current physical and electrical tests. First, we have developed new metrics that measure the effectiveness of existing test methods for detecting counterfeit defects and different counterfeit types. We have used these metrics to drive optimization algorithms that select the tests yielding the highest detection confidence under timing and cost constraints. Second, we are developing new advanced physical inspection techniques that can detect more counterfeit types non destructively, with less equipment, and with less imaging sessions. Finally, we are have developed and will continue to develop electrical tests for certain classes of parts (FPGAs, SRAMs, DRAMs, Flash, etc.) that detect counterfeits with high confidence and avoid the need to perform physical inspection.

Current and Past Project Sponsors

We are thankful for the support provided by the following government agencies and companies:

 

Books and Book Chapters

  • M. Tehranipoor, U. Guin, D. Forte, Counterfeit Integrated Circuits: Detection and Avoidance, Springer 2015. [link]
  • K. Xiao, D. Forte, and M. Tehranipoor,  “Circuit Timing Signature (CTS) for Detection of Counterfeit Integrated Circuits,” in Secure System Design and Trustable Computing, by Chip Hong Chang and Miodrag Potkonjak, 2015. [link]

Our Conference and Journal Papers

NOTE: This directory contains pdf/ps files of articles that may be covered by copyright. You may browse the articles at your convenience, in the same spirit as you may read a journal or a proceedings article in a public library. Retrieving, copying, or distributing these files may violate copyright protection laws.

Current State of Supply Chain Vulnerabilities and Countermeasures

  • X. Xu, F. Rahman, B. Shakya, A. Vassilev, D. Forte, M. Tehranipoor, “Electronics Supply Chain Integrity Enabled by Blockchain”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 24, No. 3, June 2019. [link]
  • U.J. Botero, M. Tehranipoor, D. Forte, “Upgrade/Downgrade: Efficient and Secure Legacy Electronic System Replacement”, IEEE Design & Test, Vol. 36, No. 1, February 2019. [link]
  • M.M. Alam, S. Chowdhury, B. Park, D. Munzer, N. Maghari, M. Tehranipoor, D. Forte, “Challenges and Opportunities in Analog and Mixed Signal (AMS) Integrated Circuit (IC) Security”, Journal of Hardware and Systems Security (HaSS), Vol. 2, No. 1, March 2018. [link]
  • U. Guin, D. Forte, M. Tehranipoor, “Anti-Counterfeit Techniques: From Design to Resign”, Microprocessor Test and Verification (MTV), December 2013. [pdf]

Design-for-Anti-Counterfeit (DfAC)

  • RY Acharya, M. Levin, D. Forte, “LDO-based Odometer to Combat IC Recycling”, to appear IEEE International System-on-Chip Conference (SOCC), September 2021. [pdf]
  • K. Yang, U.J. Botero, H. Shen, D. Woodard, D. Forte, M. Tehranipoor, “UCR: An Unclonable Environmentally-Sensitive Chipless RFID Tag For Protecting Supply Chain”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 23, No. 6, December 2018. [link]
  • U.J. Botero, M.Tehranipoor, D. Forte, “Downgrade: A Framework for Obsolescence Handling through Backwards Compatibility” in GOMACTech, March 2018.
  • K. Yang, D. Forte, M. Tehranipoor, “CDTA: A Comprehensive Solution for Counterfeit Detection, Traceability and Authentication in IoT Supply Chain,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 22, No. 3, April 2017. [link]
  • U. Guin, S. Bhunia, D. Forte, M. Tehranipoor, “SMA: A System-Level Mutual Authentication for Protecting Electronic Hardware and Firmware,” IEEE Transactions on Dependable and Secure Computing (TDSC), 2016. [link]
  • Z. Guo, B. Shakya, H. Shen, S. Bhunia, N. Asadizanjani, D. Forte, M. Tehranipoor, “A New Methodology to Protect PCBs from Non-destructive Reverse Engineering,” International Symposium for Testing and Failure Analysis (ISTFA), Nov. 2016. [pdf]
  • U Guin, Q. Shi, D. Forte, M. Tehranipoor, “FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 21, No. 4, June 2016. [link]
  • K. Yang, D. Forte, M. Tehranipoor, “UCR: Unclonable Chipless RFID Tag”, Hardware-Oriented Security and Trust (HOST) 2016, May 2016. [pdf] [HOST 2016 Best Paper Nomination]
  • U. Guin, D. Forte, M. Tehranipoor, “Design of Accurate Low-Cost On-Chip Structures for protecting Integrated Circuits against Recycling,” IEEE Transactions on VLSI Systems (TVLSI), Vol. 24, No. 4, April 2016. [link]
  • B. Shakya, U. Guin, M. Tehranipoor, D. Forte, “Performance Optimization for On-Chip Sensors to Detect Recycled ICs,”  IEEE International Conference on Computer Design (ICCD), Oct. 2015. [pdf]
  • K. Yang, D.Forte, M.Tehranipoor, “ReSC: RFID-enabled Supply Chain Management and Traceability for Network Devices,” 11th Work­shop on RFID Se­cu­ri­ty (RFIDSec 2015), June 2015. [pdf]
  • K. Yang, D. Forte, M. Tehranipoor, “An RFID-based Technology for Electronic Component and System Counterfeit Detection and Traceability” in IEEE International Conference on Technologies for Homeland Security (HST), April 2015. [pdf]
  • M.T. Rahman, D. Forte, Q. Shi, G. Contreras, M. Tehranipoor, “CSST: Preventing Distribution of Unlicensed and Rejected ICs by Untrusted Foundry and Assembly,” IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct. 2014. [pdf]
  • U. Guin, D. Forte, X. Zhang, M. Tehranipoor, “Low-cost On-Chip Structures for Combating Die and IC Recycling,” Design Automation Conference (DAC), June 2014. [link]
  • M.T. Rahman, D. Forte, Q. Shi, G. Contreras, M. Tehranipoor, “CSST: An Efficient Secure Split-Test for Preventing IC Piracy,” IEEE North Atlantic Test Workshop (NATW), May 2014. [link]

Advanced Physical Inspection and Electrical Tests

  • P. Ghosh, U. Botero, F. Ganji, D. Woodard, RS Chakraborty, D. Forte, “Automated Detection and Localization of Counterfeit Chip Defects by Texture Analysis in Infrared (IR) Domain”, IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE), December 2020. [pdf]
  • S. Chowdhury, F Ganji, D. Forte, “Low-Cost Remarked Counterfeit IC Detection Using LDO Regulators”, IEEE International Symposium on Circuits and Systems (ISCAS), October 2020. [pdf]
  • S. Chowdury, F. Ganji, D. Forte, “Recycled SoC Detection using LDO Degradation” , SN Computer Science, September 2020. [link]
  • A. Stern, U.J. Botero, F. Rahman,  D. Forte, M. Tehranipoor, “EMFORCED: EM-Based Fingerprinting Framework for Remarked and Cloned Counterfeit IC Detection using Machine Learning Classification”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 28, No. 2, February 2020. [link]
  • M. Alam, M. Tehranipoor, D. Forte, “Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization and Voltage Scaling”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 27, No.12, December 2019. [link]
  • S. Chowdhury, F. Ganji, T. Bryant, N. Maghari, D. Forte, “Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation”, IEEE International Test Conference (ITC), November 2019. [pdf]
  • S. Chowdhury, H. Shen, B. Park, N. Maghari, D. Forte, “Aging  Analysis  of  Low  Dropout  Regulator  for Universal  Recycled  IC  Detection”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2019. [pdf]
  • P. Ghosh, F. Ganji, D. Forte, D. Woodard, RS Chakraborty, “Automated Framework for Unsupervised Counterfeit Integrated Circuit Detection by Physical Inspection”, to appear International Conference on Physical Assurance and Inspection of Electronics (PAINE), July 2019. [pdf]
  • P. Ghosh, A. Bhattacharyay, D. Forte, RS Chakraborty, “Automated Defective Pin Detection for Recycled Microelectronics Identification”, Journal of Hardware and Systems Security (HaSS), Vol. 3, No. 3, September 2019. [link]
  • A. Stern, U.J. Botero, B. Shakya, H. Shen, D. Forte, M. Tehranipoor, “EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked ICs”, IEEE International Test Conference (ITC), October 2018. [pdf]
  • P. Ghosh, D. Forte, D. Woodard, R.S. Chakraborty, “Automated Detection of Pin Defects on Counterfeit Microelectronics”, International Symposium for Testing and Failure Analysis (ISTFA), October 2018. [pdf]
  • Z. Guo, X. Xu, M. Tehranipoor, D. Forte, “SCARe: An SRAM-based Countermeasure Against IC Recycling Framework”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 26, No. 3, April 2018. [link]
  • S. Baireddy, U.J. Botero, N. Asadi, M.Tehranipoor, D. Woodard, D. Forte, “Automated Detection of Counterfeit IC Defects Using Image Processing” in GOMACTech, March 2018.
  • Z. Guo, M. Tehranipoor, D. Forte,”Memory-based Counterfeit IC Detection Framework”, SRC TECHCON, Sept. 2017.
  • Z. Guo, X. Xu, M. Tehranipoor, D. Forte, “FFD: A Framework for Fake Flash Detection”, Design Automation Conference (DAC), June 2017. [link]
  • M. Alam, H. Shen, N. Asadi, M. Tehranipoor, D. Forte, “Impact of X-ray Tomography on the Reliability of Integrated Circuits”, IEEE Transactions on Device and Materials Reliability (TDMR), Vol. 17, No. 1, March, 2017. [link]
  • M. M. Alam, M. Tehranipoor, D. Forte, “Recycled FPGA Detection Using Exclusive LUT Path Delay Characterization,” IEEE International Test Conference (ITC), Nov. 2016. [pdf]
  • N. Asadizanjani, D. Forte, M. Tehranipoor, “Non-destructive Bond Pull and Ball Shear Failure Analysis Based on Real Structural Properties,” International Symposium for Testing and Failure Analysis (ISTFA), Nov. 2016. [pdf]
  • N. Asadizanjani, S. Gattigowda, N. Dunn, M. Tehranipoor, D. Forte, “A Database for Counterfeit Electronics and Automatic Defect Detection Based on Image Processing and Machine Learning,” International Symposium for Testing and Failure Analysis (ISTFA), Nov. 2016. [pdf]
  • Z. Guo, M. T. Rahman, M. Tehranipoor, D. Forte, “A Zero-cost Approach to Detect Recycled SoCs Using Embedded SRAM”, Hardware-Oriented Security and Trust (HOST) 2016, May 2016. [pdf]
  • H. Dogan, M. Alam, N. Asadizanjani, S. Shahbazmohamadi, D. Forte,  M. Tehranipoor, “Analyzing the Impact of X-ray Tomography for Non-destructive Counterfeit Detection”, International Symposium for Testing and Failure Analysis (ISTFA), Nov. 2015. [pdf]
  • S. Shahbazmohamadi, D. Forte, M. Tehranipoor, “Advanced Physical Inspection Methods for Counterfeit Detection”, International Symposium for Testing and Failure Analysis (ISTFA), Nov. 2014. [pdf]
  • H. Dogan, D. Forte, M. Tehranipoor, “Aging Analysis for Recycled FPGA Detection,” IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct. 2014. [pdf]