Publications

Publications

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Books

  1. M. Tehranipoor, D. Forte, G. Rose, S. Bhunia, Security Opportunities in Nano Devices and Emerging Technologies, CRC Press, 2017. [link]
  2. D. Forte, S. Bhunia, M. Tehranipoor, Hardware Protection through Obfuscation, Springer, 2017. [link]
  3. M. Tehranipoor, U. Guin, D. Forte, Counterfeit Integrated Circuits: Detection and Avoidance, Springer 2015. [link] 

Book Chapters

  1. A. Covic, S. Chowdhury, RY Acharya, F. Ganji, D. Forte, “Post-Quantum Hardware Security: Physical Security in Classic vs. Quantum Worlds,” in Emerging Topics in Hardware Security by Mark M. Tehranipoor, Springer, 2020. [link]
  2. H. Lu, DE Capecci, P. Ghosh, D. Forte, DL Woodard, “Computer Vision for Hardware Security,” in Emerging Topics in Hardware Security, Mark M. Tehranipoor, Springer, 2021. [link]
  3. Q. Shi, D. Forte, M. Tehranipoor, “Deterrent Approaches Against Hardware Trojan Insertion,” in The Hardware Trojan War: Attacks, Myths, and Defenses, Swarup Bhunia and Mark M. Tehranipoor, Springer, 2018. [link]
  4. F. Rahman, A. Nath, D. Forte, S. Bhunia, and M Tehranipoor, “Nano CMOS Logic-Based Security Primitive Design”, in Security Opportunities in Nano Devices and Emerging Technologies by Mark M. Tehranipoor, Domenic Forte, Garrett Rose, and Swarup Bhunia, CRC Press, 2017. [link]
  5. H.T. Shen, F. Rahman, M. Tehranipoor, D. Forte, “Carbon-Based Novel Devices for Hardware Security”, in Security Opportunities in Nano Devices and Emerging Technologies by Mark M. Tehranipoor, Domenic Forte, Garrett Rose, and Swarup Bhunia, CRC Press, 2017. [link]
  6. F. Rahman, A. Nath, S. Bhunia, D. Forte, M. Tehranipoor, “Composition of Physical Unclonable Functions: From Device to Architecture”, in Security Opportunities in Nano Devices and Emerging Technologies by Mark M. Tehranipoor, Domenic Forte, Garrett Rose, and Swarup Bhunia, CRC Press, 2017. [link]
  7. B. Shakya, X. Xu, N. Asadizanjani, M. Tehranipoor, D. Forte, “Leveraging Circuit Edit for Low-Volume Trusted Nanometer Fabrication”, in Security Opportunities in Nano Devices and Emerging Technologies by Mark M. Tehranipoor, Domenic Forte, Garrett Rose, and Swarup Bhunia, CRC Press, 2017. [link]
  8. B. Shakya, M. Tehranipoor, S. Bhunia, D. Forte, “Introduction to Hardware Obfuscation: Motivation, Methods and Evaluation,” in Hardware Protection through Obfuscation by Domenic Forte, Swarup Bhunia, and Mark M. Tehranipoor, Springer, 2017. [link]
  9. Z. Guo, M. Tehranipoor, D. Forte, “Permutation-Based Obfuscation,” in Hardware Protection through Obfuscation by Domenic Forte, Swarup Bhunia, and Mark M. Tehranipoor, Springer, 2017. [link]
  10. M. T. Rahman, D. Forte, M. Tehranipoor, “Protection of Assets from Scan Chain Vulnerabilities through Obfuscation,” in Hardware Protection through Obfuscation by Domenic Forte, Swarup Bhunia, and Mark M. Tehranipoor, Springer, 2017. [link]
  11. Q. Shi, K. Xiao, D. Forte, M. Tehranipoor, “Obfuscated Built-in Self Authentication,” in Hardware Protection through Obfuscation by Domenic Forte, Swarup Bhunia, and Mark M. Tehranipoor, Springer, 2017. [link]
  12. A. Nahiyan, K. Xiao, D. Forte, M. Tehranipoor, “Security Rule Check,” in Hardware IP Security and Trust by Prabhat Mishra, Swarup Bhunia and Mark Tehranipoor, Springer, 2017. [link]
  13. Q. Shi, D. Forte, M. Tehranipoor, “Analyzing Circuit Layout to Probing Attack,” in Hardware IP Security and Trust by Prabhat Mishra, Swarup Bhunia and Mark Tehranipoor, Springer, 2017. [link]
  14. K. Xiao, D. Forte, M. Tehranipoor,  “Circuit Timing Signature (CTS) for Detection of Counterfeit Integrated Circuits,” in Secure System Design and Trustable Computing, by Chip Hong Chang and Miodrag Potkonjak, 2016. [link]

Journal (accepted)

  1. D. Forte, B. Amaba, C. Richards, J. Daniels, “Nowhere to Hide: Monitoring Side-channels for Supply Chain Resiliency”, IEEE Reliability Magazine, 2024. [pdf]
  2. M. Gao, L. Biswas, N. Asadi, D. Forte, “Detour–RS: Reroute Attack Vulnerability Assessment with Awareness of Layout and Resource”, to appear Cryptography, 2024. [pdf]
  3. P. Ghosh, G. Lee, M. Zhu , O. Dizon-Paradis, UJ Botero, D. Woodard, D. Forte, “MaGNIFIES: Manageable GAN Image Augmentation Framework for Inspection of Electronic Systems” to appear Journal of Hardware and Systems Security (HaSS), 2024. [pdf]
  4. J. Wu, D. Forte, “EXERTv2: Exhaustive Integrity Analysis for Information Flow Security with FSM Integration”, to appear Journal of Hardware and Systems Security (HaSS), 2023. [pdf]
  5. R. Wilson, O. Dizon-Paradis, D. Forte, D. Woodard, “SECURE: A Segmentation Quality Evaluation Metric on SEM images for Reverse Engineering on Integrated Circuits”, IEEE Access, 2023. [link]
  6. M. Gao, MS Rahman, N. Varshney, M. Tehranipoor, D. Forte, “iPROBE: Internal Shielding Approach for Protecting Against Front-side and Back-side Probing Attack,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 42, No. 12, December 2023. [pdf]
  7. D. Koblah, UJ Botero, SP Costello, O. Paradis, F. Ganji, D. Woodard, D. Forte, “A Fast Object Detection-Based Framework for Via Modeling on PCB X-Ray CT Images”, ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 19, No. 4, October 2023. [link]
  8. M. Choudhury, M. Gao, A. Varna, E. Peer, D. Forte, “Enhanced PATRON: Fault Injection and Power-aware FSM Encoding Through Linear Programming”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 28, No. 6, October 2023. [link]
  9. R. Acharya, F. Ganji, D. Forte, “Information Theory-based Evolution of Neural Networks for Side-channel Analysis”, IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), September 2023. [link]
  10. D. Koblah, O. Dizon-Paradis, J. Schubeck, UJ Botero, D. Woordard D. Forte, “A Comprehensive Taxonomy of Visual Printed Circuit Board Defects,” Journal of Hardware and Systems Security (HaSS), April 2023. [link]
  11. T. Bryant, Y. Chen, D. Koblah, D. Forte, N. Maghari, “A Brief Tutorial on Mixed Signal Approaches to Combat Electronic Counterfeiting,” IEEE Open Journal of Circuits and Systems, Vol. 4, March 2023. [link]
  12. T. Farheen, S. Roy, S. Tajik, D. Forte, “A Twofold Clock and Voltage-based Detection Method for Laser Logic State Imaging Attack”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 31, No. 1, January 2023. [pdf]
  13. D. Koblah, R. Acharya,  D. Capecci, O. Dizon-Paradis, S. Tajik, F. Ganji, D. Woodard, D. Forte, “A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 28, No. 2, March 2023. [preprint] [link]
  14. S. Amir and D. Forte, “EigenCircuit: Divergent Synthetic Benchmark Generation for Hardware Security Using PCA and Linear Programming”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 41, No. 12, December 2022. [pdf] [link]
  15. Y. Bai, A. Stern, J. Park, M. Tehranipoor, D. Forte, “RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems “, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 27, No. 1, Nov. 2022. [pdf] [link]
  16. Y. Bai, J. Park, M. Tehranipoor, D. Forte, “Real-time Instruction-level Verification of Remote IoT/CPS Devices Via Side Channels”, Discover Internet of Things Journal, Vol. 2, No. 1, March 2022. [pdf]
  17. S. Shomaji, P. Ghosh, F. Ganji, DL Woodard, D. Forte, “”An Analysis of Enrollment and Query Attacks on Hierarchical Bloom Filter-based Biometric Systems”, IEEE Transactions on Information Forensics and Security (TIFS), Vol. 16, Nov. 2021. [pdf]
  18. B. Park, D. Forte, M. Tehranipoor, N. Maghari, “A Metal-Via Resistance based Physically Unclonable Function with Backend Incremental ADC”, IEEE Transactions on Circuits and Systems I, Vol 68, No. 11, Nov. 2021. [pdf]
  19. S. Shomaji, Z. Guo, F. Ganji, N. Karimian, DL Woodard, D. Forte, “”BLOcKeR: A Biometric Locking Paradigm for IoT and the Connected Person”, Journal of Hardware and Systems Security (HaSS), Vol. 5, No. 3, Oct. 2021. [link]
  20. S. Shomaji, NVR Masna, DJ Ariando, SD Paul, K. Horace-Herron, D. Forte, S. Mandal, S. Bhunia, “Detecting Dye-Contaminated Vegetables using Low-Field NMR Relaxometry”, Foods, Vol. 10, No. 9, Sept. 2021. [pdf]
  21. R. Wilson, H. Lu, M. Zhu, D. Forte, DL Woodard, “”REFICS: Assimilating Data-Driven Paradigms into Reverse Engineering and Hardware Assurance on Integrated Circuits”, IEEE Access, Vol. 9, Sept. 2021. [pdf]
  22. UJ Botero, R. Wilson, H. Lu, MT Rahman, MA Mallaiyan, F. Ganji, N. Asadizanjanizanjani, MM Tehranipoor, DL Woodard, D. Forte, “Hardware Trust and Assurance through Reverse Engineering: A Tutorial and Outlook from Image Analysis and Machine Learning Perspectives”, ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 17, No. 4, June 2021. [preprint] [link]
  23. MS Rahman, A. Nahiyan, F. Rahman, S. Fazzari, K. Plaks, F. Farahmandi, D. Forte, M. Tehranipoor, “”Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks”‘, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 26, No. 4, March 2021. [link]
  24. S. Chowdhury, A. Covic, R. Acharya, S. Dupee, F. Ganji, D. Forte, “Physical Security in the Post-quantum Era: A Survey on Side-channel Analysis, Random Number Generators, and Physically Unclonable Functions”, Journal of Cryptographic Engineering (JCEN), 2021. [link]
  25. H. Wang, Q. Shi, A. Nahiyan, D. Forte, M. Tehranipoor, “A Physical Design Flow against Front-side Probing Attacks by Internal Shielding”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 39, No. 10, October 2020. [link]
  26. S. Chowdury, F. Ganji, D. Forte, “Recycled SoC Detection using LDO Degradation”, SN Computer Science, September 2020. [link]
  27. N. Karimian, D. Woodard, D. Forte, “ECG Biometric: Spoofing and Countermeasures”, IEEE Transactions on Biometrics, Behavior, and Identity Science (T-BIOM), Vol. 2, No. 3, July 2020. [link]
  28. M. Alam, A. Nahiyan, M. Sadi, D. Forte, M. Tehranipoor, “Soft-HaT: Software-based Silicon Reprogramming for Hardware Trojan Implementation,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 25, No. 4, June 2020. [link]
  29. F. Ganji, S. Tajik, P. Stauss, J.-P. Seifert, M. Tehranipoor, D. Forte, “Rock’n’roll PUFs: Crafting Provably Secure PUFs from Less Secure Ones (Extended Version),” Journal of Cryptographic Engineering (JCEN), May 2020. [link]
  30. A. Nahiyan, J. Park, H. Miao, Y. Iskander, F. Farahmandi, D. Forte, M. Tehranipoor, “SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment using Information Flow Tracking and Pattern Generation”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 25, No. 3, May 2020. [link]
  31. MT Rahman, MS Rahman, H. Wang, S. Tajik, W. Khalil, F. Farahmandi, D. Forte, N. Asadizanjani, M. Tehranipoor, “Defense-in-Depth: A Recipe for Logic Locking to Prevail”, Integration, the VLSI Journal, Vol. 72, May 2020. [link]
  32. A. Stern, U.J. Botero, F. Rahman,  D. Forte, M. Tehranipoor, “EMFORCED: EM-Based Fingerprinting Framework for Remarked and Cloned Counterfeit IC Detection using Machine Learning Classification”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 28, No. 2, February 2020. [link]
  33. Z. Guo, S. Chowdury, M. Tehranipoor, D. Forte, “Permutation Network De-obfuscation: A Delay-based Attack and Countermeasure Investigation”, ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 16, No. 2, January 2020. [link]
  34. B. Shakya, X. Xu, M. Tehranipoor, D. Forte, “CAS-Lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme”, IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), No. 1, 2020. [link]
  35. J. Park, F. Rahman, A. Vassilev, D. Forte, M. Tehranipoor, “Leveraging Side-channel Information for Disassembly and Security”, ACM Journal on Emerging Technologies in Computing (JETC), Vol. 16, No. 1, December 2019. [link]
  36. T. Hoque, K. Yang, R. Karam, S. Tajik, D. Forte, M. Tehranipoor, S. Bhunia, “Hidden in Plaintext: An Obfuscation-based Countermeasure against FPGA Bitstream Tampering Attacks”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 25, No. 1, December 2019. [link]
  37. M. Alam, M. Tehranipoor, D. Forte, “Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization and Voltage Scaling”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 27, No.12, December 2019. [link]
  38. F. Ganji, D. Forte, JP Seifert, “PUFmeter: A Property Testing Tool for Assessing the Robustness of Physically Unclonable Functions to Machine Learning Attacks”, IEEE Access, Vol. 7, No. 1, December 2019. [link]
  39. BM Talukder, B. Ray, D. Forte, MT Rahman, “PreLatPUF: Exploiting DRAM Latency Variations for Generating Robust Device Signatures”, IEEE Access, Vol. 7, No. 1, December 2019. [link]
  40. N. Karimain, M. Tehranipoor, D. Woodard, D. Forte, “Unlock Your Heart: Next Generation Biometric in Resource-Constrained Healthcare Systems and IoT”, IEEE Access, Vol. 7, No. 1, December 2019. [link]
  41. S. Shomaji, P. Dehghanzadeh, A. Roman, D. Forte, S. Bhunia, S. Mandal, “Early Detection of Cardiovascular Diseases Using Wearable Ultrasound Device”, IEEE Consumer Electronics Magazine, Vol. 8, No. 6, November 2019. [link]
  42. Q. Shi, M. Tehranipoor, D. Forte, “Obfuscated Built-In Self-Authentication with Secure and Efficient Wire-Lifting”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 38, No. 11, November 2019. [link]
  43. P. Ghosh, A. Bhattacharyay, D. Forte, RS Chakraborty, “Automated Defective Pin Detection for Recycled Microelectronics Identification” Journal of Hardware and Systems Security (HaSS), Vol. 3, No. 3, September 2019. [link]
  44. B. Shakya, H. Shen, M. Tehranipoor, D. Forte, “Covert Gates: Protecting Integrated Circuits with Undetectable Camouflaging”, IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), August 2019 [link]
  45. X. Xu, F. Rahman, B. Shakya, A. Vassilev, D. Forte, M. Tehranipoor, “Electronics Supply Chain Integrity Enabled by Blockchain”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 24, No. 3, June 2019. [link]
  46. H. Wang, Q. Shi. D. Forte, M. Tehranipoor, “Probing Assessment Framework and Evaluation of Anti-probing Solutions”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 27, No. 6, June 2019. [link]
  47. A. Nahiyan, F. Farahmandi, P. Mishra, D. Forte, M. Tehranipoor, “Security-aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 38, No. 6, June 2019. [link]
  48. F. Ganji, D. Forte, N. Asadizanjani, M. Tehranipoor, D. Woodard, “The Power of IC Reverse Engineering for Hardware Trust and Assurance”, Electronic Device Failure Analysis (EDFA), May 2019. [link]
  49. F. Ganji, N. Karimian, D. Woodard, D. Forte, “Leave Adversaries in the Dark- BLOcKeR: Secure and Reliable Biometric Access Control”, The Journal of the Homeland Defense and Security Information Analysis Center (HDIAC), Vol. 6, No. 1, Spring 2019. [link]
  50. U.J. Botero, M. Tehranipoor, D. Forte, “Upgrade/Downgrade: Efficient and Secure Legacy Electronic System Replacement”, IEEE Design & Test, Vol. 36, No. 1, February 2019. [link]
  51. K. Yang, U.J. Botero, H. Shen, D. Woodard, D. Forte, M. Tehranipoor, “UCR: An Unclonable Environmentally-Sensitive Chipless RFID Tag For Protecting Supply Chain”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 23, No. 6, December 2018. [link]
  52. X. Xu, S. Keshavarz, D. Forte, M. Tehranipoor, D.E. Holcomb, “Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 26, No. 11, November 2018. [link]
  53. S. Amir, B. Shakya, X. Xu, Y. Jin, S. Bhunia, M. Tehranipoor, D. Forte, “Development and Evaluation of Hardware Obfuscation Benchmarks”, Journal of Hardware and Systems Security (HaSS), Vol. 2, No. 2, June 2018. [link]
  54. Z. Guo, X. Xu, M. Tehranipoor, D. Forte, “SCARe: An SRAM-based Countermeasure Against IC Recycling Framework”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 26, No. 3, April 2018. [link]
  55. M.M. Alam, S. Chowdhury, B. Park, D. Munzer, N. Maghari, M. Tehranipoor, D. Forte, “Challenges and Opportunities in Analog and Mixed Signal (AMS) Integrated Circuit (IC) Security”, Journal of Hardware and Systems Security (HaSS), Vol. 2, No. 1, March 2018. [link]
  56. K. Yang, D. Forte, M. Tehranipoor, “ReSC: An RFID-Enabled Solution for Defending IoT Supply Chain”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 23, No. 3, February 2018. [link]
  57. K. Yang, H. Shen, D. Forte, S. Bhunia, M. Tehranipoor, “Hardware-Enabled Pharmaceutical Supply Chain Security”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 23, No. 3, January 2018. [link]
  58. F. Rahman, B. Shakya, X. Xu, D. Forte, M. Tehranipoor, “Security Beyond CMOS: Fundamentals, Applications, and Roadmap”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 25, No. 12, December 2017. [link]
  59. H. Shen, F. Rahman, B. Shakya, X. Xu, M. Tehranipoor, D. Forte, “Poly-Si Based Physical Unclonable Functions”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 25, No. 11, November 2017. [link]
  60. E.L. Principe, N. Asadizanjani, D. Forte, M. Tehranipoor, R. Chivas, M. DiBattista, S. Silverman, “Plasma FIB Deprocessing of Integrated Circuits from the Backside”, Electronic Device Failure Analysis (EDFA), Vol. 19, No. 4, November 2017. [link]
  61. H. Wang, Q. Shi, D. Forte, M. Tehranipoor, “Probing Attacks on Integrated Circuits: Challenges and Research Opportunities”, IEEE Design & Test, Vol. 34, No. 5, October 2017. [link]
  62. M.T. Rahman, A. Hosey, Z. Guo, J. Carroll, D. Forte, M. Tehranipoor, “Systematic Correlation and Cell Neighborhood Analysis of SRAM-PUF for Robust and Unique Key Generation,” Journal of Hardware and Systems Security (HaSS), Vol. 1, No. 2, June 2017. [link]
  63. N. Karimian, Z. Guo, M. Tehranipoor, D. Forte, “Highly Reliable Key Generation from Electrocardiogram (ECG)” IEEE Transactions on Biomedical Engineering, Vol. 64, No. 6, June 2017. [link]
  64. U. Guin, S. Bhunia, D. Forte, M. Tehranipoor, “SMA: A System-Level Mutual Authentication for Protecting Electronic Hardware and Firmware,” IEEE Transactions on Dependable and Secure Computing (TDSC), Vol. 14, No. 3, May-June 1 2017. [link]
  65. Z. Guo, J. Di, M. Tehranipoor, D. Forte, “Obfuscation-based Protection Framework Against Printed Circuit Boards Unauthorized Operation and Reverse Engineering”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 22, No. 3, April 2017. [link]
  66. K. Yang, D. Forte, M. Tehranipoor, “CDTA: A Comprehensive Solution for Counterfeit Detection, Traceability and Authentication in IoT Supply Chain,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 22, No. 3, April 2017. [link]
  67. B. Shakya, T. He, H. Salmani, D. Forte, S. Bhunia, M. Tehranipoor, “Benchmarking of Hardware Trojans and Maliciously Affected Circuits”, Journal of Hardware and Systems Security (HaSS), Vol. 1, No. 1, April 2017. [link]
  68. M. Alam, H. Shen, N. Asadizanjani, M. Tehranipoor, D. Forte, “Impact of X-ray Tomography on the Reliability of Integrated Circuits”, IEEE Transactions on Device and Materials Reliability (TDMR), Vol. 17, No. 1, March 2017. [link]
  69. N. Asadizanjani, M. Tehranipoor, D. Forte, “PCB Reverse Engineering Using Non-destructive X-ray Tomography and Advanced Image Processing”, IEEE Transactions on Components, Packaging and Manufacturing (CPMT), Vol. 7, No. 2, February 2017. [link]
  70. N. Asadizanjani, M. Tehranipoor,  D. Forte, “Counterfeit electronics detection using image processing and machine learning”, Journal of physics: conference series, Vol. 787, No. 1, February 2017. [link]
  71. K. Xiao, D. Forte, Y. Jin, R. Karri, S. Bhunia, M. Tehranipoor, “Hardware Trojans: Lessons Learned After One Decade of Research”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 22, No. 1, June 2016. [link] [2018 ACM TODAES Best Paper, ACM Computing Reviews Notable Computing Books and Articles 2016, Hardware Category]
  72. U Guin, Q. Shi, D. Forte, M. Tehranipoor, “FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 21, No. 4, June 2016 [link]
  73. U. Guin, D. Forte, M. Tehranipoor, “Design of Accurate Low-Cost On-Chip Structures for protecting Integrated Circuits against Recycling,” IEEE Transactions on VLSI Systems (TVLSI), Vol. 24, No. 4, April 2016. [link]
  74. S. E. Quadir, J. Chen, D. Forte, N. Asadizanjani, S. Shahbazmohamadi, L. Wang, J. Chandy, M. Tehranipoor, “A Survey on Chip to System Reverse Engineering,” ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 13, No.1, April 2016. [link]
  75. C. Bao, D. Forte, A. Srivastava, “On Reverse Engineering-Based Hardware Trojan Detection,”  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 34, No. 10, January 2016 [link]
  76. C. Bao, D. Forte, A. Srivastava, “Temperature Tracking: Towards Robust Run-time Detection of Hardware Trojans,”  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 34, No. 10, October 2015 [link]
  77. M.T. Rahman, F. Rahman, D. Forte, M. Tehranipoor, “An Aging-Resistant RO-PUF for Reliable Key Generation,” IEEE Transactions on Emerging Topics in Computing (TETC), September 2015. [link]
  78. A. Mazady, M.T. Rahman, D. Forte, M. Anwar, “Memristor Nano-PUF A Security Primitive: Theory and Experiment,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS),    Vol. 5, No. 2, June 2015. [link]
  79. K. Xiao, D. Forte, M. Tehranipoor, “A Novel Built-In Self Authentication Technique to Prevent Inserting Hardware Trojans”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 33, No. 12, December 2014. [link]
  80. D. Forte, A. Srivastava, “Improving the Quality of Delay-based PUFs via Optical Proximity Correction”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 32, No. 12, December 2013 . [link]
  81. D. Forte, A. Srivastava, “Thermal-Aware Sensor Scheduling for Distributed Estimation”, ACM Transactions on Sensor Networks (TOSN), Vol. 9, No. 4, November 2013. [link]
  82. D. Forte, A. Srivastava, “Energy and Thermal-Aware Video Coding via Encoder/Decoder Workload Balancing”, ACM Transactions on Embedded Computing Systems (TECS), Vol. 12, No. 2, May 2013. [link]
  83. D. Forte, A. Srivastava, “Resource-Aware Architectures for Adaptive Particle Filter Based Visual Target Tracking”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, No. 2, April 2013. [link]

Conference & Workshop (accepted)

  1. T. Farheen, S. Roy, A. Cannon, J. Di, S. Tajik, D. Forte, “Amnesiac Memory: A Self-Destructive Polymorphic Mechanism Against Cold Boot Data Remanence Attack”, to appear GLSVLSI, June 2024. []
  2. T. Farheen, S. Roy, J. Di, S. Tajik, D. Forte, “Calibratable Polymorphic Temperature Sensor for Detecting Side channel and Fault Injection Attacks”, to appear IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2024. [pdf]
  3. J. Wu, O. Dizon-Paradis, S. Rahman, D. Woodard, D. Forte, “DOSCrack: Deobfuscation using Oracle-guided Symbolic Execution and Clustering of Binary Security Keys”, to appear IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2024. [pdf]
  4. H. Wang, M. Panoff, Z. Zhan, S. Wang, C. Bobda and D. Forte, “Programmable EM Sensor Array for Golden-Model Free Run-time Trojan Detection and Localization”, to appear Design, Automation and Test in Europe Conference (DATE), March 2024. [eprint]
  5. M. Hashemi, D. Forte, F. Ganji, “Time Is Money, Friend! Timing Side-channel Attack against Garbled Circuit Constructions” to appear Applied Cryptography and Network Security (ACNS), March 2024. [eprint] [pdf]
  6. D. Koblah, D. Mehta, M. Hashemi, F. Ganji, D. Forte, “EDA Workflow for Optimization of Robust Model Probing-Compliant Masked Hardware Gadgets”, GOMACTech, March 2024. [pdf]
  7. D. Koblah, R. Acharya, D. Forte, “Genetic Algorithm for Functionally-Equivalent and Structurally-Divergent Benchmark Generation”, GOMACTech, March 2024. [pdf]
  8. A. Cannon, T. Farheen, S. Roy, S. Tajik, D. Forte, “Protection Against Physical Attacks Through Self-Destructive Polymorphic Latch”, International Conference on Computer-Aided Design (ICCAD), November 2023. [pdf] 
  9. MM Rizvee, T. Hossain. T. Hoque, D. Forte, S. Shomaji, “A Persistent Hierarchical Bloom Filter-based Framework for Authentication and Tracking of ICs”, IEEE International Workshop On Silicon Lifecycle Management, October 2023. []
  10. R. Holzhausen, T. Farheen, M. Thomas, N. Maghari, D. Forte, “Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic Cells”, International Test Conference (ITC), October 2023. [pdf]
  11. P. Ghosh, S. Shomaji, D. Woodard, D. Forte, “KinfaceNet: A New Deep Transfer Learning based Kinship Feature Extraction Framework”,  IEEE International Joint Conference on Biometrics (IJCB 2023), September 2023. [pdf]
  12. H. Wang, M. Panoff, S. Wang, D. Forte, ““HT-EMIS: A Deep Learning Tool for Hardware Trojan Detection and Identification through Runtime EM Side-Channels”, Great Lakes Symposium on VLSI (GLSVLSI), June 2023. [pdf]
  13. M. Gao, D. Forte, “Detour: Layout-aware Reroute Attack Vulnerability Assessment and Analysis”, Hardware-Oriented Security and Trust (HOST), May 2023. [pdf]
  14. Y. Bai, J. Park, M. Tehrnaipoor, D. Forte, “Dual Channel EM/Power Attack Using Mutual Information and its Real-time Implementation” Hardware-Oriented Security and Trust (HOST), May 2023. [pdf]
  15. S. Roy, S. Tajik, D. Forte, “Polymorphic Sensor to Detect Laser Logic State Imaging Attack” International Symposium on Quality Electronic Design (ISQED), April 2023. [pdf]
  16. T. Farheen, S. Tajik, D. Forte, “SPRED: Spatially Distributed Laser Fault Injection Resilient Design” International Symposium on Quality Electronic Design (ISQED), April 2023. [pdf]
  17. S.Roy, J. Chen, D. Forte, “Self-contained LDO Odometer to Detect Recycled Counterfeit AMS Chips”, in GOMACTech, March 2023. [pdf]
  18. J. Wu, F. Fowze, D. Forte, “EXERT: EXhaustive IntEgRiTy Analysis for Information Flow Security”, IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), December 2022. [pdf]
  19. F. Fowze, M. Choudhury, D. Forte, “EISec: Exhaustive Information Flow Security of Hardware Intellectual Property Utilizing Symbolic Execution”, IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), December 2022. [pdf]
  20. M. Gao, D. Forte, “iPROBE-O: FIB-aware Place and Route for Probing Protection Using Orthogonal Shields” IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), December 2022. [pdf]
  21. M. Hashemi, S. Roy, D. Forte, F. Ganji, “HWGN2: Side-channel Protected NNs through Secure and Private Function Evaluation” International Conference on Security, Privacy and Applied Cryptographic Engineering  (SPACE), December 2022. [link]
  22. D. Koblah, F. Ganji, D. Forte, S. Tajik, “Hardware Moving Target Defenses against Physical Attacks: Design Challenges and Opportunities”, ACM Workshop on Moving Target Defense (MTD), November 2022. [link]
  23. M. Hashemi, S. Roy, F, Ganji, D. Forte, ““Garbled EDA: Privacy-Preserving Electronic Design Automation”, International Conference on Computer-Aided Design (ICCAD), November 2022. [preprint]
  24. M. Choudhury, M. Gao, S. Tajik, D. Forte, “TAMED: Transitional Approaches for LFI Resilient State Machine Encoding”, IEEE International Test Conference (ITC), September 2022. [pdf]
  25. S. Roy, M. Hashemi, F. Ganji, D. Forte, “Active IC Metering Protocol Security Revisited and Enhanced with Oblivious Transfer”, SRC TECHCON, September 2022. [pdf]
  26. RY Acharya, D. Forte, “Joint Optimization of NCL PUF Using Frequency-based Analysis and Evolutionary Algorithm”, International Symposium on Quality Electronic Design (ISQED), April 2022. [pdf]
  27. S. Roy, T. Farheen, S. Tajik, D. Forte, “Self-timed Sensors for Detecting Static Optical Side Channel Attacks”, International Symposium on Quality Electronic Design (ISQED), April 2022. [pdf]
  28. J. Schubeck, D. Koblah, U. Botero, D. Forte, “A Comprehensive Taxonomy of PCB Defects”, in GOMACTech, March 2022. [pdf]
  29. R. Wilson, H. Lu, M. Zhu, D. Forte, DL Woodard, “REFICS: A Step Towards Linking Vision with Hardware Assurance”, Winter Conference on Applications of Computer Vision (WACV), January 2022. [pdf]
  30. U. Botero, F. Ganji, D. Woodard, D Forte, “Automated Trace and Copper Plane Extraction of X-ray Tomography Imaged PCBs”, IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE), December 2021. [pdf]
  31. T. Farheen, U. Botero, N. Varshney, HT Shen, DL Woodard, M. Tehranipoor, D. Forte, “Proof of Reverse Engineering Barrier: SEM Image Analysis on Covert Gates”, International Symposium for Testing and Failure Analysis (ISTFA), November 2021. [pdf]
  32. M. Choudhury, S. Tajik, D. Forte, “SPARSE: Spatially Aware LFI Resilient State Machine Encoding”, Hardware and Architectural Support for Security and Privacy (HASP), October 2021. [pdf] [link]
  33. RY Acharya, M. Levin, D. Forte, “LDO-based Odometer to Combat IC Recycling”, IEEE International System-on-Chip Conference (SOCC), September 2021. [pdf]
  34. RY Acharya, N. Charlot, MM Alam, F. Ganji, D. Gauthier, D. Forte, “Chaogate Parameter Optimization using Bayesian Optimization and Genetic Algorithm”,  International Symposium on Quality Electronic Design (ISQED’21), April 2021. [pdf]
  35. DS Koblah, UJ Botero, F. Ganji, D. Woodard, D. Forte, “Via Modeling on X-Ray Images of Printed Circuit Boards Through Deep Learning”, in GOMACTech, March 2021.
  36. J. Bellay, D. Forte, R. Martin, C. Taylor, “Hardware Vulnerability Description, Sharing and Reporting: Challenges and Opportunities”, in GOMACTech, March 2021. [pdf]
  37. M. Choudhury, S. Tajik, D. Forte, “PATRON: A Pragmatic Approach for Encoding LFI Resistant FSMs”, Design, Automation and Test in Europe (DATE), February 2021. [preprint]
  38. R. Acharya, S. Chowdhury, F Ganji, D. Forte, “Attack of the Genes: Finding Keys and Parameters of Locked Analog ICs Using Genetic Algorithm” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), December 2020. [preprint]
  39. U. Botero, F. Ganji, N. Asadizanjani, D.Woodard, D. Forte, “Semi-Supervised Automated Layer Identification of X-ray Tomography Imaged PCBs”, IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE), December 2020. [pdf]
  40. P. Ghosh, U. Botero, F. Ganji, D. Woodard, RS Chakraborty, D. Forte, “Automated Detection and Localization of Counterfeit Chip Defects by Texture Analysis in Infrared (IR) Domain”, IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE), December 2020. [pdf]
  41. UJ Botero, D. Koblah, DE Capecci, F. Ganji, N. Asadi, DL Woodard, D. Forte, “Automated Via Detection for PCB Reverse Engineering”, International Symposium for Testing and Failure Analysis (ISTFA), December 2020. [pdf] [EDFAS Virtual Workshop (ISTFA 2020) Outstanding Paper Award]
  42. R. Wilson, D. Forte, N. Asadi, D. Woodard, “LASRE: A Novel Approach to Large area Accelerated Segmentation for Reverse Engineering on SEM images”, International Symposium for Testing and Failure Analysis (ISTFA), December 2020. [preprint]
  43. S. Chowdhury, R. Acharya, W. Boullion, M. Howard, A. Felder, J. Di, D. Forte, “A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates”, IEEE International Test Conference (ITC), November 2020. [preprint]
  44. S. Amir, D. Forte, “Adaptable and Divergent Synthetic Benchmark Generation for Hardware Security”, International Conference on Computer-Aided Design (ICCAD), November 2020. [pdf]
  45. S. Chowdhury, F Ganji, D. Forte, “Low-Cost Remarked Counterfeit IC Detection Using LDO Regulators”, IEEE International Symposium on Circuits and Systems (ISCAS), October 2020. [pdf]
  46. A. Covic, F. Ganji, D. Forte, “Circuit Masking Schemes: New Hope for Backside Probing Countermeasures?”, SRC TECHCON, September 2020.
  47. M. Gao, H. Wang, M. Tehranipoor, D. Forte, “iPROBE V2: Internal Shielding-based Countermeasures against Both Back-side and Front-side Probing Attacks”, SRC TECHCON, September 2020.
  48. F Ganji, S. Amir, S. Tajik, D. Forte, JP Seifert, “Pitfalls in Machine Learning-based Adversary Modeling for Hardware Systems”, Design, Automation, and Test in Europe (DATE), March 2020. [preprint]
  49. UJ Botero, N. Asadizanjani, D. Woodard, D. Forte, “A Framework for Automated Alignment and Layer Identification of X-Ray Tomography Imaged PCBs”, in GOMACTech, March 2020. [link]
  50. A. Covic, Q. Shi, H. Shen, D. Forte, “Contact-to-Silicide Probing Attacks on Integrated Circuits and Countermeasures”, IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), December 2019. [pdf]
  51. A. Alaql, D. Forte, S.Bhunia, “Sweep to the Secret: A Constant Propagation Attack on Logic Locking”, IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), December 2019. [pdf]
  52. S. Chowdhury, F. Ganji, T. Bryant, N. Maghari, D. Forte, “Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation”, IEEE International Test Conference (ITC), November 2019. [pdf]
  53. R. Wilson, RY Acharya, D. Forte, N. Asadizanjani, D. Woodard, “A Novel Approach to Unsupervised Automated Extraction of Standard Cell Library for Reverse Engineering and Hardware Assurance”, International Symposium for Testing and Failure Analysis (ISTFA), November 2019. [pdf]
  54. S. Shomaji, F. Ganji, D. Woodard, D. Forte, “Hierarchical Bloom Filter Framework for Security, Space-efficiency, and Rapid Query Handling in Biometric Systems”, IEEE International Conference on Biometrics: Theory, Applications and Systems (BTAS), September 2019. [pdf]
  55. M. Alam, S. Tajik, F. Ganji, M. Tehranipoor, D. Forte, “RAM-Jam: Remote Temperature and Voltage Fault Attack on FPGAs using Memory Collisions”, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), August 2019. [link]
  56. F. Ganji, S. Tajik, P. Stauss, JP Seifert, D. Forte, M. Tehranipoor, “Approaches for Hardness Amplification of PUFs”, International Workshop on Security Proofs for Embedded Systems (PROOFS), August 2019. [preprint]
  57. R. Wilson, N. Asadizanjani, D. Forte, D. Woodard, “First Auto-Magnifier Platform for Hardware Assurance and Reverse Engineering Integrated Circuits”, Microscopy & Microanalysis (M&M), August 2019. [link]
  58. P. Ghosh, F. Ganji, D. Forte, D. Woodard, RS Chakraborty, “Automated Framework for Unsupervised Counterfeit Integrated Circuit Detection by Physical Inspection”, International Conference on Physical Assurance and Inspection of Electronics (PAINE), July 2019. [pdf]
  59. S. Chowdhury, H. Shen, B. Park, N. Maghari, D.Forte, “Aging Analysis of Low Dropout Regulator for Universal Recycled IC Detection”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2019. [pdf]
  60. A. Gorbenko, N. Noor, S. Muneer, R. Khan, F. Dirisaglik, A. Cywar, B. Shakya, D. Forte, M. van Dijk, A. Gokirmak, H. Silva, “Resistance Drift and Crystallization in Suspended and On-Oxide Phase Change Memory Line Cells”, IEEE International Conference on Nanotechnology (IEEE-NANO), July 2019. [link]
  61. B. Park, M. Tehranipoor, D. Forte, N. Maghari, “A Metal-Via Resistance Based Physically Unclonable Function with 1.18% Native Instability” IEEE Custom Integrated Circuits Conference (CICC), April 2019. [pdf]
  62. A. Alaql, T. Hoque, D. Forte, S. Bhunia, “Quality Obfuscation for Reliable and Adaptive Hardware IP Protection”, IEEE VLSI Test Symposium (VTS), April 2019. [pdf]
  63. A. Stern, K. Yang, J. Vosatka, A. Duncan, J. Park, D. Forte, M. Tehranipoor, “RASC: Enabling Remote Access to Side-Channels for Mission Critical Systems”, in GOMACTech, March 2019.
  64. Q. Shi, H. Wang, N. Asadizanjani, M. Tehranipoor, D. Forte, “A Comprehensive Analysis on Vulnerability of Active Shields to Tilted Microprobing Attacks”, IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), December 2018. [pdf]
  65. A. Stern, U.J. Botero, B. Shakya, H. Shen, D. Forte, M. Tehranipoor, “EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked ICs”, IEEE International Test Conference (ITC), October 2018. [pdf]
  66. H. Shen, N. Asadizanjani, M. Tehranipoor, D. Forte, “Nanopyramid: An Optical Scrambler Against Backside Probing Attacks”, International Symposium for Testing and Failure Analysis (ISTFA), October 2018. [pdf]
  67. P. Ghosh, D. Forte, D. Woodard, R.S. Chakraborty, “Automated Detection of Pin Defects on Counterfeit Microelectronics”, International Symposium for Testing and Failure Analysis (ISTFA), October 2018. [pdf]
  68. H. Wang, Q. Shi, N. Asadizanjani, D. Forte, M. Tehranipoor, “A Physical Design Flow against Front-side Probing Attacks by Internal Shielding”, SRC TECHCON, September 2018.
  69. J. Park, X. Xu, Y. Jin, D. Forte, M. Tehranipoor, “Power-based Side-Channel Instruction-level Disassembler”, Design Automation Conference (DAC), June 2018. [link]
  70. E.L. Principe, N. Asadizanjani, D. Forte, M. Tehranipoor, M. DiBattista, R. Chivas, S. Silverman, N. Piche, M. Marsh, J. Mastovich, “Steps Toward Computational Guided Deprocessing of Integrated Circuits” in GOMACTech, March 2018.
  71. D. Capecci, G. Contreras, D. Forte, M.Tehranipoor, S. Bhunia, “Automated SoC Security from Design to Fabrication” in GOMACTech, March 2018.
  72. S. Baireddy, U.J. Botero, N. Asadizanjani, M.Tehranipoor, D. Woodard, D. Forte, “Automated Detection of Counterfeit IC Defects Using Image Processing” in GOMACTech, March 2018.
  73. U.J. Botero, M.Tehranipoor, D. Forte, “Downgrade: A Framework for Obsolescence Handling through Backwards Compatibility” in GOMACTech, March 2018.
  74. S. Chowdhury, X. Xu, M. Tehranipoor, D. Forte, “Aging Resistant RO PUF with Increased Reliability in FPGA”,  International Conference on Reconfigurable Computing and FPGAs (ReConFig), December 2017. [pdf]
  75. E.L. Principe, N.Asadizanjani, D. Forte, M. Tehranipoor, R. Chivas, M. DiBattista, S.Silverman, M. Marsh, N. Piche, J. Mastovich, “Steps Toward Automated Deprocessing of Integrated Circuits,”  International Symposium for Testing and Failure Analysis (ISTFA), November 2017. [pdf] [ISTFA 2017 Outstanding Paper Award]
  76. A. Chhotaray, A. Nahiyan, T. Shrimpton, D. Forte, M. Tehranipoor, “Standardizing Bad Cryptographic Practice – A Teardown of the IEEE Standard for Protecting Electronic-Design Intellectual Property,” ACM Conference on Computer and Communications Security (CCS), November 2017. [link]
  77. A. Nahiyan, M. Sadi, R. Vittal, G. Contreras, D. Forte, M.Tehranipoor, “Hardware Trojan Detection through Information Flow Security Verification,” IEEE International Test Conference (ITC), November 2017. [pdf]
  78. Z. Guo, X. Xu, M. Tehranipoor, D. Forte, “MPA: Model-assisted PCB Attestation via Board-level RO and Temperature Compensation”, IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), October 2017. [pdf]
  79. K. Yang, U.J. Botero, H. Shen, D. Forte, M. Tehranipoor, “A Split Manufacturing Approach for Unclonable Chipless RFIDs for Pharmaceutical Supply Chain Security”, IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), October 2017. [pdf]
  80. N. Karimian, D. Woodard, D. Forte, “On the Vulnerability of ECG Verification to Online Presentation Attacks”, International Joint Conference on Biometrics (IJCB), October 2017. [pdf] [IJCB 2017 Best Student Paper Award]
  81. X. Xu, B. Shakya, M. Tehranipoor, D. Forte, “Novel Bypass Attack and BDD-based Tradeoff Analysis Against all Known Logic Locking Attacks,” International Conference on Cryptographic Hardware and Embedded Systems (CHES), September 2017. [link]
  82. Z. Guo, M. Tehranipoor, D. Forte,”Memory-based Counterfeit IC Detection Framework”, SRC TECHCON, September 2017.
  83. Z. Guo, X. Xu, M. Tehranipoor, D. Forte, “FFD: A Framework for Fake Flash Detection”, Design Automation Conference (DAC), June 2017. [link]
  84. Q. Shi, K. Xiao, D. Forte, M. Tehranipoor, “Securing Split Manufactured ICs with Wire Lifting Obfuscated Built-In Self-Authentication”, GLSVLSI, May 2017. [link]
  85. S. Amir, B. Shakya, D. Forte, M. Tehranipoor, S. Bhunia, “Comparative Analysis of Hardware Obfuscation for IP Protection”, GLSVLSI, May 2017. [link]
  86. T. Byrant, S. Chowdhury, D. Forte, M. Tehranipoor, N. Maghari, “A Stochastic All-Digital Weak Physically Unclonable Function for Analog/Mixed-Signal Applications”, IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), May 2017. [pdf]
  87. N. Karimian, F. Tehranipoor, Z. Guo, M. Tehranipoor, D. Forte, “Noise Assessment Framework for Optimizing ECG Key Generation”, IEEE International Conference on Technologies for Homeland Security (HST), April 2017. [pdf]
  88. Q. Shi, N. Asadizanjani, D. Forte, M.Tehranipoor, “Layout-based Microprobing Vulnerability Assessment for Security Critical Applications,” in GOMACTech, March 2017.
  89. N. Karimian, Z. Guo, M. Tehranipoor, D. Forte, “Human Recognition from Photoplethysmography (PPG) Based on Non-fiducial Features”, IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), March 2017. [pdf]
  90. N. Karimian, M. Tehranipoor, D. Forte, “Non-Fiducial PPG-based Authentication for Healthcare Application”, International Conference on Biomedical and Health Informatics (BHI), February 2017. [pdf]
  91. G. K. Contreras, A. Nahiyan, S. Bhunia, D. Forte, M. Tehranipoor, “Security Vulnerability Analysis of Design-for-Test Exploits for Asset Protection in SoCs,” Asia and South Pacific Design Automation Conference (ASP-DAC), January 2017. [link]
  92. Z. Guo, M. Tehranipoor, D. Forte, “Aging Attacks for Key Extraction on Permutation-Based Obfuscation,” IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), December 2016. [pdf]
  93. T. Rahman, D. Forte, X. Wang, M. Tehranipoor, “Enhancing Noise Sensitivity of Embedded SRAMs for Robust True Random Number Generation in SoCs,” IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), December 2016. [pdf]
  94. M. M. Alam, M. Tehranipoor, D. Forte, “Recycled FPGA Detection Using Exclusive LUT Path Delay Characterization,” IEEE International Test Conference (ITC), November 2016. [pdf]
  95. B. Shakya, N. Asadizanjani, D. Forte, M. Tehranipoor, “Chip Editor: Leveraging Circuit Edit for Logic Obfuscation and Trusted Fabrication,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2016. [link]
  96. Z. Guo, B. Shakya, H. Shen, S. Bhunia, N. Asadizanjani, D. Forte, M. Tehranipoor, “A New Methodology to Protect PCBs from Non-destructive Reverse Engineering,” International Symposium for Testing and Failure Analysis (ISTFA), November 2016. [pdf]
  97. N. Asadizanjani, D. Forte, M. Tehranipoor, “Non-destructive Bond Pull and Ball Shear Failure Analysis Based on Real Structural Properties,” International Symposium for Testing and Failure Analysis (ISTFA), November 2016. [pdf]
  98. N. Asadizanjani, S. Gattigowda, N. Dunn, M. Tehranipoor, D. Forte, “A Database for Counterfeit Electronics and Automatic Defect Detection Based on Image Processing and Machine Learning,” International Symposium for Testing and Failure Analysis (ISTFA), November 2016. [pdf]
  99. T. Bryant, S. Chowdhury, D. Forte, M. Tehranipoor, N. Maghari, “A Stochastic Approach to Analog Physical Unclonable Function,” IEEE Midwest Symposium on Circuits and Systems (MWSCAS), October 2016. [pdf]
  100. M. T. Rahman, D. Forte, and M. Tehranipoor, “SRAM Inspired Design and Optimization for Developing Robust Security Primitives,” in SRC TECHCON, September 2016. [Awarded Best in Session]
  101. N. Karimian, M. Tehranipoor, D. Woodard, D. Forte, “Biometrics for Authentication in Resource-Constrained Systems,” International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), August 2016. [link]
  102. H. Shen, F. Rahman, B. Shakya, M. Tehranipoor, D. Forte, “Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs)”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2016. [pdf]
  103. A. Nahiyan, K. Xiao, K. Yang, Y. Jin, D. Forte, M. Tehranipoor, “AVFSM: A Framework for Identifying and Mitigating Vulnerabilities in FSMs”, Design Automation Conference (DAC), June 2016. [link]
  104. Z. Guo, N. Karimian, M. Tehranipoor, D. Forte, “Hardware Security Meets Biometrics for the Age of IoT”, IEEE International Symposium on Circuits and Systems (ISCAS), May 2016. [pdf]
  105. T. Le, J. Di, M. Tehranipoor, D. Forte, L. Wang, “Tracking Data Flow at Gate-Level through Structural Checking”, GLSVLSI, May 2016. [link]
  106. Q. Shi, N. Asadizanjani, D. Forte, M.Tehranipoor, “A Layout-driven Framework to Assess Vulnerability of ICs to Microprobing Attacks”, IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), May 2016. [pdf] [HOST 2016 Best Paper Award] 
  107. Z. Guo, M. T. Rahman, M. Tehranipoor, D. Forte, “A Zero-cost Approach to Detect Recycled SoCs Using Embedded SRAM”, IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), May 2016. [pdf]
  108. K.Yang, D. Forte, M. Tehranipoor, “UCR: Unclonable Chipless RFID Tag”, IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), May 2016. [pdf]  [HOST 2016 Best Paper Nomination] 
  109. F. Rahman, D. Forte, and Mark Tehranipoor, “Reliability vs. Security: Challenges and Opportunities for Developing Reliable and Secure Integrated Circuits,” International Reliability Physics Symposium (IRPS), April 2016 [pdf] (Invited Paper).
  110. M. M. Alam, N. Asadizanjani, M.Tehranipoor, D. Forte, “The Impact of X-ray Tomography on the Reliability of FPGAs” in GOMACTech, March 2016.
  111. Z. Guo, N. Karimian, M. Tehranipoor, D. Forte, “Biometric Based Human-to-Device (H2D) Authentication”, in GOMACTech, March 2016.
  112. N. Asadizanjani, S. Shahbazmohamadi, D. Forte, M. Tehranipoor, “Nondestructive X-ray Tomography Based Bond Pull and Ball Shear Analysis” in GOMACTech, March 2016.
  113. B. Shakya, F. Rahman, M. Tehranipoor, D. Forte, “Harnessing Nanoscale Device Properties for Hardware Security”,  Microprocessor Test and Verification (MTV), December 2015. [pdf]
  114. K. Yang, D. Forte, M. Tehranipoor, “Protecting Endpoint Devices in IoT Supply Chain”,  IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2015. [link]
  115. H. Dogan, M. Alam, N. Asadizanjani, S. Shahbazmohamadi, D. Forte,  M. Tehranipoor, “Analyzing the Impact of X-ray Tomography for Non-destructive Counterfeit Detection”, International Symposium for Testing and Failure Analysis (ISTFA), November 2015. [pdf]
  116. N. Asadizanjani, S. Shahbazmohamadi, M. Tehranipoor, D. Forte, “Non-destructive PCB Reverse Engineering Using X-ray Micro Computed Tomography”, International Symposium for Testing and Failure Analysis (ISTFA), November 2015. [pdf]
  117. B. Shakya, U. Guin, M. Tehranipoor, D. Forte, “Performance Optimization for On-Chip Sensors to Detect Recycled ICs,” IEEE International Conference on Computer Design (ICCD), October 2015. [pdf]
  118. M. T. Rahman, D. Forte, F. Rahman, M. Tehranipoor, “A Pair Selection Algorithm for Robust RO-PUF Against Environmental Variations and Aging,” IEEE International Conference on Computer Design (ICCD), October 2015. [pdf]
  119. S. Chen, J. Chen, D. Forte, J. Di, M. Tehranipoor, L. Wang, “Chip-level Anti-reverse Engineering using Transformable Interconnects,” IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), October 2015. [pdf]
  120. M. T. Rahman, D. Forte, and M. Tehranipoor, “Robust SRAM-PUF: Cell Stability Analysis and Novel Bit-Selection Algorithm,” SRC TECHCON, September 2015.
  121. K. Yang, D.Forte, M.Tehranipoor, “ReSC: RFID-enabled Supply Chain Management and Traceability for Network Devices,” in 11th Work­shop on RFID Se­cu­ri­ty (RFIDSec 2015), June 2015. [pdf]
  122. Z. Guo, J. Di, M. Tehranipoor, D. Forte, “Investigation of Obfuscation-based Anti-Reverse Engineering for Printed Circuit Boards,” Design Automation Conference (DAC) 2015, June 2015. [link]
  123. K. Xiao, D. Forte, M. Tehranipoor, “Efficient and Secure Split Manufacturing via Obfuscated Built-In Self-Authentication,” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) 2015, May 2015. [pdf] [HOST 2015 Best Paper Award] 
  124. N. Karimian, F. Tehranipoor, M.T. Rahman, S. Kelly, D. Forte, “Genetic Algorithm for Hardware Trojan Detection with Ring Oscillator Network (RON),” IEEE International Conference on Technologies for Homeland Security (HST), April 2015. [pdf]
  125. K. Yang, D. Forte, M. Tehranipoor, “An RFID-based Technology for Electronic Component and System Counterfeit Detection and Traceability,” IEEE International Conference on Technologies for Homeland Security (HST), April 2015.[pdf]
  126. M.T. Rahman, A. Hosey, F. Rahman, D. Forte, M. Tehranipoor, “RePa: A Pair Selection Algorithm for Reliable Keys from RO-based PUF” GOMACTech, March 2015.
  127. H. Dogan, D. Forte, M. Tehranipoor, “Aging Analysis for Recycled FPGA Detection” GOMACTech, March 2015.
  128. N. Asadizanjani, S. E. Quadir, S. Shahbazmohamadi, M. Tehranipoor, D. Forte, “Rapid Non-destructive Reverse Engineering of Printed Circuit Boards by High Resolution X-ray Tomography” GOMACTech, March 2015.
  129. A. Hosey, M.T. Rahman, K. Xiao, D. Forte, M. Tehranipoor, “Advanced Analysis of Cell Stability for Reliable SRAM PUF,” IEEE Asian Test Symposium (ATS), November 2014 [pdf]
  130. S. Shahbazmohamadi, D. Forte, M. Tehranipoor, “Advanced Physical Inspection Methods for Counterfeit Detection”, International Symposium for Testing and Failure Analysis (ISTFA), November 2014. [pdf]
  131. M.T. Rahman, D. Forte, Q. Shi, G. Contreras, M. Tehranipoor, “CSST: Preventing Distribution of Unlicensed and Rejected ICs by Untrusted Foundry and Assembly,” IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), October 2014. [pdf]
  132. H. Dogan, D. Forte, M. Tehranipoor, “Aging Analysis for Recycled FPGA Detection,” IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), October 2014. [pdf]
  133. U. Guin, D. Forte, X. Zhang, M. Tehranipoor, “Low-cost On-Chip Structures for Combating Die and IC Recycling,” Design Automation Conference (DAC), June 2014 [link]
  134. M.T. Rahman, K. Xiao, D. Forte, X. Zhang, Z. Shi, M. Tehranipoor, “TI-TRNG: Technology Independent True Random Number Generator,” Design Automation Conference (DAC), June 2014 [link]
  135. M.T. Rahman, D. Forte, Q. Shi, G. Contreras, M. Tehranipoor, “CSST: An Efficient Secure Split-Test for Preventing IC Piracy,” IEEE North Atlantic Test Workshop (NATW), May 2014 [link]
  136. K. Xiao, M.T. Rahman, D. Forte, M. Su, Y. Huang, M.Tehranipoor, “Bit Selection Algorithm Suitable for High-Volume Production of SRAM-PUF,” in IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), May 2014 [pdf]
  137. U. Guin, D. Forte, M. Tehranipoor, “Low-cost On-Chip Structures for Combatting Die and IC Recycling,” in GOMACTech, April 2014.
  138. K. Xiao, M.T. Rahman, D. Forte, M.Tehranipoor, “Low-cost Analysis for Identification of Mass-Produced Electronic Devices,” in GOMACTech, April 2014.
  139. U. Guin, D. Forte, D. DiMase, M. Tehranipoor, “Counterfeit IC Detection: Test Method Selection Considering Test Time, Cost, and Tier Level Risks,” in GOMACTech, April 2014.
  140. C. Bao, D. Forte, A. Srivastava, “On Application of One-class SVM to Reverse Engineering-Based Hardware Trojan Detection”, International Symposium on Quality Electronic Design (ISQED), March 2014. [pdf]
  141. M.T. Rahman, D. Forte, J. Fahrny, M. Tehranipoor, “ARO-PUF: An Aging-Resistant Ring Oscillator PUF Design,” Design, Automation, & Test in Europe (DATE), March 2014. [pdf]
  142. U. Guin, D. Forte, M. Tehranipoor, “Anti-Counterfeit Techniques: From Design to Resign”, Microprocessor Test and Verification (MTV), December 2013. [pdf]
  143. D. Forte, C. Bao, A. Srivastava, “Temperature Tracking: An Innovative Run-Time Approach for Hardware Trojan Detection”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2013. [pdf]
  144. D. Forte, A. Srivastava, “Manipulating Manufacturing Variations for Better Silicon-Based Physically Unclonable Functions”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), August  2012. [link]
  145. D. Forte, A. Srivastava, “On Improving the Uniqueness of Silicon-Based Physically Unclonable Functions Via Optical Proximity Correction”, Design Automation Conference (DAC), June 2012. [DAC 2012 Best Paper Nomination] [link]
  146. D. Forte, A. Srivastava, “Energy-Aware and Quality-Scalable Data Placement and Retrieval for Disks in Video Server Environments”, IEEE International Conference on Computer Design (ICCD), October 2011. [link]
  147. D. Forte, A. Srivastava, “Adaptable Architectures for Distributed Visual Target Tracking”, IEEE International Conference on Computer Design (ICCD) , October 2011. [link]
  148. D. Forte, A. Srivastava, “Energy-Aware Video Storage and Retrieval in Server Environments”, International Green Computing Conference and Workshops (IGCC), July 2011. [link]
  149. D. Forte, A. Srivastava, “Resource-Aware Architectures for Particle Filter Based Visual Target Tracking”, International Green Computing Conference and Workshops (IGCC), July 2011. [link]
  150. D. Forte, A. Srivastava, “Adaptable Video Compression and Transmission using Lossy and Workload Balancing Techniques”, NASA/ESA Conference on Adaptive Hardware and Systems (AHS), June 2011 [Awarded AHS-2011 Best Student Paper] [link]
  151. D. Forte, A. Srivastava, “Energy-Aware Video Coding of Multiple Views via Workload Balancing”, NASA/ESA Conference on Adaptive Hardware and Systems (AHS), June 2011. [link]
  152. D. Forte, A.Srivastava, “Energy and Thermal-Aware Video Coding via Encoder/Decoder Workload Balancing”, International Symposium on Low Power Electronics and Design (ISLPED), August 2010. [link]
  153. D. Forte, A. Srivastava, “Thermal-Aware Sensor Scheduling for Distributed Estimation”, International Conference on Distributed Computing in Sensor Systems (DCOSS), June 2010. [link]

Patents

  1. D.Woodard, D. Forte, N. Asadizanjani, R. Wilson. “Accelerated Segmentation for Reverse Engineering of Integrated Circuits”, granted on February 6, 2024.
  2. F. Ganji, S. Tajik, JP Seifert, D. Forte, M. Tehranipoor, “Hardness Amplification of Physical Unclonable Functions (PUFs)”, granted on October 24, 2023.
  3. D. Woodard, N. Asadizanjani, D. Forte, R. Wilson. “Automatic Sharpness Adjustment for Imaging Modalities”, granted on October 2, 2023.
  4. S. Chowdhury, F. Ganji, N. Maghari, D. Forte, “Detection Of Recycled Integrated Circuits And System-On-Chips Based On Degradation Of Power Supply Rejection Ratio”, granted on May 23, 2023.
  5. M. Tehranipoor, U. Guin, D. Forte, “A Comprehensive Framework for Protecting Intellectual Property in Semiconductor Industry”, granted on March 21, 2023.
  6. H. Shen, N. Asadizanjani, D. Forte, M. Tehranipoor, “Optical Scrambler With Nano-Pyramids”, granted on November 22, 2022.
  7. M. Tehranipoor, A. Nahiyan, J. Park, D. Forte, “CAD Framework for Power Side-channel Vulnerability Assessment”, granted on October 18, 2022.
  8. S. Chowdhury, D. Forte, M. Levin, N. Maghari, “LDO-Based Odometer To Combat IC Recycling”, published on June 22, 2022.
  9. D. Forte, D. Woodard, F. Ganji, S. Shomaji. “Biometric Locking Methods and Systems for Internet of Things and the Connected Person”, published on June 16, 2022.
  10. M. Tehranipoor, A. Nahiyan, D. Forte, “Hardware Trojan Detection Through Information Flow Security Verification”, granted on March 8, 2022.
  11. D. Woodard, R. Wilson, N. Asadizanjani, D. Forte. “Histogram-based Auto Segmentation: A Novel Approach to Segmenting Integrated Circuit Structures from SEM Images”, granted on March 8, 2022.
  12. M. Tehranipoor, D. Forte, F. Farahmandi, A. Nahiyan, F. Rahman, MS Rahman, “Protecting Obfuscated Circuits Against Attacks That Utilize Test Infrastructures”, granted on January 11, 2022.
  13. D. Woodard, R. Wilson, N. Asadizanjani, D. Forte, “Method and Apparatus for Automatic Extraction of Standard Cells to Generate a Standard Cell Candidate Library”, granted on October 26, 2021.
  14. M. Tehranipoor, H. Wang, Q. Shi, H. Shen, D. Forte. “Prevention of Front-side Probing Attacks”, granted on August 10, 2021.
  15. B. Shakya, H. Shen, M. Tehranipoor, D. Forte, “Covert Gates To Protect Gate-Level Semiconductors”, granted on July 6, 2021.
  16. M. Tehranipoor, D. Forte, B. Shakya, and  N. Asadizanjani, “Circuit Edit and Obfuscation for Trusted Chip Fabrication”, granted on June 8, 2021.
  17. M. Tehranipoor, K. Yang, H. Shen, U. Botero, D. Forte, “Cross-Registration For Unclonable Chipless RFID Tags”, granted on February 23, 2021.
  18. M. Tehranipoor, D. Forte, N. Asadizanjani, Q. Shi, “Layout-Driven Method to Assess Vulnerability of ICs To Microprobing Attacks”, granted on February 25, 2020.
  19. S. Bhunia, H. Shen, M. Tehranipoor, D. Forte, N. Asadizanjani, “Vanishing via for hardware IP protection from reverse engineering” granted on May 7, 2019.
  20. M. Tehranipoor, K. Yang, H. Shen, D. Forte, “Unclonable Environmentally-sensitive Chipless RFID Tag with a Plurality of Slot Resonators”, granted on January 15, 2019.

Editorials

  1. D. Forte, D. Mukhopadhyay, I.Polian, Y. Fe, R.Cammarota, “Introduction to the Special Issue on Emerging Challenges and Solutions in Hardware Security”, ACM Journal on Emerging Technologies in Computing Systems, Vol. 17, No. 3,  July 2021. [link]
  2. D. Forte, Y. Iskander,  “Guest editorial: Hardware Reverse Engineering and Obfuscation”, Journal of Hardware and Systems Security (HaSS), Vol. 2, No. 4 [link]
  3. D. Forte, R. Perez, Y. Kim, S. Bhunia,  “Guest editors’ introduction: Supply-Chain Security for Cyberinfrastructure”, IEEE Computer, Vol. 49, No. 8, August 2016. [link]

Other

  1. J. Bellay, D.Forte, Bob Martin, J. Boyens, “Chapter 1: Hardware Assurance and Weakness Collaboration and Sharing (HAWCS)”, Trusted and Assured MicroElectronics Working Groups Report, December 2019. [link]
  2. D. Forte, S. Bhunia, R. Karri, J. Plusquellic, M. Tehranipoor, “IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future”, IEEE International Test Conference (ITC), November 2019. [link]

Dissertation

  1. D. Forte, “Design, Fabrication, and Run-time Strategies for Hardware-Assisted Security”, Ph.D. dissertation, Dept. of Electrical and Computer Engineering, University of Maryland, May 2013. [link]