Design and Fabrication of Hardware Security Primitives

The security of computing and information systems relies on well-established primitives for key generation and management, message confidentiality and integrity, authentication, oblivious transfer, bit commitment, etc. However, the classic algorithms are slow, expensive, and increasingly vulnerable to physical and side channel attacks. Recently, hardware-based security primitives such as physically unclonable functions (PUFs) and true random number generators (TRNGs) have been proposed to overcome these limitations.

A physically unclonable function (PUF) is a structure that when interrogated by a challenge (input) generates a unique device response (output) that depends on the randomness of the PUF structure created by manufacturing variations. should be intractable for an adversary to create a hardware or software clone of a PUF. PUFs with a large input-output space are considered “strong” and can be used in various authentication protocols. A physical obfuscated key (POK) is a “weak” version of a PUF in the sense that its input/output space is small. POKs can store cryptographic keys that are less vulnerable to physical attacks. The open challenges in PUF research include practical solutions for PUF reliability over temporal variations (voltage variation, temperature variations, silicon aging, etc.), susceptibility to machine learning attacks, and susceptibility to side channel attacks.

A true-random number generator (TRNG) is a component designed to produce a sequence of symbols that appear indistinguishable from one generated by a uniform distribution. TRNGs operate by measuring a physical phenomenon expected to be random, such as thermal noise or other quantifiable electromagnetic and quantum phenomena. TRNGs are widely used for confidentiality (one time pads, session keys, seeds, initial vectors, etc.), integrity (e.g., nonce generation), and authenticity (challenges for authentication, etc.). The main challenges in TRNG research include low-cost designs that are robust against manipulation of environment (voltage and temperature) and silicon aging.

In our work, we have addressed many shortcomings of existing PUF and TRNG research including:

  1. PUF Fabrication and Materials Optimization:While the existence of variations has been well exploited in PUF design, knowledge of exactly how variations come into existence has largely been ignored. Existing  work merely assumes the variations to be a black box. Yet, for several decades the design-for-manufacturability (DFM) community has actually investigated the fundamental sources of these variations. Since manufacturing variations are often harmful to IC yield, tools developed by DFM have focused on suppressing them. However, this can be counter-intuitive for PUFs which can actually benefit from random variations. In our work, we have expanded the role of EDA tools into cyber security in order to fabricate PUFs with greater randomness and reliability. Specifically, we have proposed fab-friendly techniques based on Optical Proximity Correction (OPC) and designer-friendly techniques that suppress systematic variations and enhance random variations. In addition, we have developed models for improving randomness of transistor threshold voltage and effective mobility at device materials level by employing poly-Si as substrate material. All of our approaches are compatible with CMOS processing and can be performed selectively in regions associated with the PUF.
  2. Intrinsic Memory-based PUF Enrollment and Reliability: PUFs based on intrinsic memory have the benefit that they are already contained within a system or system-on-chip (SoC). Thus, they incur little if any overhead. However, their performance is also limited by the fact that they are typically commercial-off-the-shelf and not custom designed for use as PUFs. In our work, we have investigated ways to improve PUFs that are based on traditional memories such as SRAM, Flash, and DRAM. Our low-cost enrollment algorithms select the ‘best’ cells for each memory technology based on correlated behavior in cell neighborhoods, environmental conditions, and time. All our techniques have been validated with real silicon chips. Results indicate significant improvements to SRAM, Flash, and DRAM PUF reliability at extreme voltage variations, temperature variations, and post-aging.
  3. Analog/Mixed Signal (AMS) Applicable PUF: We have designed weak PUFs that employ dynamic latched comparators and their random input offset voltages to create a chip-specific identifier. The proposed PUF can be used in analog/mixed-signal (AMS) chips due to the analog characteristics of the comparators employed. Because comparators are a fundamental block in AMS applications, the proposed PUF can reuse comparators in an AMS chip to generate unique identifiers with minimal hardware overhead. Additionally, the comparators tested in this work can be created with digital components, making this PUF suitable for use in digital chips as well. The proposed PUF has been fabricated using a 0.13 μm CMOS process. Measurements show that the PUF achieves good uniqueness and reliability across a wide range of temperatures and voltages, and with low area footprint.
  4. Aging Resistant RO-PUF: The majority of existing work focuses on improving PUF robustness against voltage supply noise and temperature. While the degradation PUFs due to silicon aging is well known, there has been little work towards developing PUFs that are inherently less sensitive to aging effects. In our work, we have studied the effects of NBTI and HCI on ring oscillator (RO)-PUF reliability and developed  the first aging resistant RO-PUF. Simulation results demonstrate that our aging resistant RO-PUF (called ARO-PUF) can produce unique, random, and more reliable keys. The ARO-PUF has about 4.5 times less errors after 10 years than the conventional RO PUF. With lower error, we estimate that the ARO-PUF obtains ~24 times area reduction for a 128-bit key due to the reduced error correction (ECC) overhead. Our pair selection algorithms determine the best ROs to use in the PUF for the lowest sensitivity to noise and best long term reliability.
  5. Technology Independent TRNG: TRNGs rely heavily on random physical phenomena such as thermal noise, shot noise, clock jitter, etc. to generate random numbers. With continued semiconductor scaling, these random phenomena are growing which can be beneficial for TRNGs. However, many military and aerospace applications rely on older and more mature technologies due to reliability concerns. We have proposed improved TRNG designs that amplify random noise to obtain better TRNG performance in older technologies.
  6. TRNG Attack Detection and Response: The bitstreams provided by TRNG can become less random (more predictable) at certain voltages/temperatures and over time (due to aging). We have developed techniques that detect bias in a TRNG that could be caused by attack manipulation and aging. Whenever bias is detected, compensation mechanisms are triggered to make the TRNG output uniformly random once again

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Our Conference and Journal Papers

NOTE: This directory contains pdf/ps files of articles that may be covered by copyright. You may browse the articles at your convenience, in the same spirit as you may read a journal or a proceedings article in a public library. Retrieving, copying, or distributing these files may violate copyright protection laws.

Surveys on Hardware Security Primitives

  • S. Chowdhury, A. Covic, R. Acharya, S. Dupee, F. Ganji, D. Forte, “Physical Security in the Post-quantum Era: A Survey on Side-channel Analysis, Random Number Generators, and Physically Unclonable Functions”, Journal of Cryptographic Engineering (JCEN), 2021. [link]

Design of Anti-Tamper and Anti-RE Sensors

  • T. Farheen, S. Roy, A. Cannon, J. Di, S. Tajik, D. Forte, “Amnesiac Memory: A Self-Destructive Polymorphic Mechanism Against Cold Boot Data Remanence Attack”, to appear GLSVLSI, June 2024. []
  • T. Farheen, S. Roy, J. Di, S. Tajik, D. Forte, “Calibratable Polymorphic Temperature Sensor for Detecting Side channel and Fault Injection Attacks”, to appear IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2024. [pdf]
  • A. Cannon, T. Farheen, S. Roy, S. Tajik, D. Forte, “Protection Against Physical Attacks Through Self-Destructive Polymorphic Latch”, International Conference on Computer-Aided Design (ICCAD), November 2023. [pdf] 
  • M. Gao, D. Forte, “Detour: Layout-aware Reroute Attack Vulnerability Assessment and Analysis”, Hardware-Oriented Security and Trust (HOST), May 2023. [pdf]
  • S. Roy, S. Tajik, D. Forte, “Polymorphic Sensor to Detect Laser Logic State Imaging Attack”, International Symposium on Quality Electronic Design (ISQED), April 2023. [pdf]
  • M. Gao, D. Forte, “iPROBE-O: FIB-aware Place and Route for Probing Protection Using Orthogonal Shields” IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), December 2022. [pdf]
  • D. Koblah, F. Ganji, D. Forte, S. Tajik, “Hardware Moving Target Defenses against Physical Attacks: Design Challenges and Opportunities”, ACM Workshop on Moving Target Defense (MTD), November 2022. [link]
  • T. Farheen, S. Roy, S. Tajik, D. Forte, “A Twofold Clock and Voltage-based Detection Method for Laser Logic State Imaging Attack”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2022. [pdf]
  • S. Roy, T. Farheen, S. Tajik, D. Forte, “Self-timed Sensors for Detecting Static Optical Side Channel Attacks”, International Symposium on Quality Electronic Design (ISQED), April 2022. [pdf]
  • H. Wang, Q. Shi, A. Nahiyan, D. Forte, M. Tehranipoor, “A Physical Design Flow against Front-side Probing Attacks by Internal Shielding”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 39, No. 10, October 2020. [link]
  • M. Gao, H. Wang, M. Tehranipoor, D. Forte, “iPROBE V2: Internal Shielding-based Countermeasures against Both Back-side and Front-side Probing Attacks”, SRC TECHCON, September 2020.

Design, Fabrication, and Evaluation of Physically Unclonable Functions (PUFs)

  • RY Acharya, D. Forte, “Joint Optimization of NCL PUF Using Frequency-based Analysis and Evolutionary Algorithm”, International Symposium on Quality Electronic Design (ISQED), April 2022. [pdf]
  • B. Park, D. Forte, M. Tehranipoor, N. Maghari, “A Metal-Via Resistance based Physically Unclonable Function with Backend Incremental ADC”, IEEE Transactions on Circuits and Systems I, 2021. [pdf]
  • S. Chowdhury, R. Acharya, W. Boullion, M. Howard, A. Felder, J. Di, D. Forte, “A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates”, IEEE International Test Conference (ITC), November 2020. [preprint]
  • F. Ganji, S. Tajik, P. Stauss, J.-P. Seifert, M. Tehranipoor, and D. Forte, “Rock’n’ roll PUFs: Crafting Provably Secure PUFs from Less Secure Ones (Extended Version),” Journal of Cryptographic Engineering (JCEN), May 2020. [link]
  • F. Ganji, D. Forte, JP Seifert, “PUFmeter: A Property Testing Tool for Assessing the Robustness of Physically Unclonable Functions to Machine Learning Attacks”, IEEE Access, December 2019. [link]
  • BM Talukder, B. Ray, D. Forte, MT Rahman, “PreLatPUF: Exploiting DRAM Latency Variations for Generating Robust Device Signatures”, IEEE Access, Vol. 7, No. 1, December 2019. [link]
  • F. Ganji, S. Tajik, P. Stauss, JP Seifert, D. Forte, M. Tehranipoor, “Approaches for Hardness Amplification of PUFs”, International Workshop on Security Proofs for Embedded Systems (PROOFS), August 2019. [preprint]
  • B. Park, M. Tehranipoor, D. Forte, N. Maghari, “A Metal-Via Resistance Based Physically Unclonable Function with 1.18% Native Instability” IEEE Custom Integrated Circuits Conference (CICC), April 2019. [pdf]
  • X. Xu, S. Keshavarz, D. Forte, M. Tehranipoor, D.E. Holcomb, “Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 26, No. 11, November 2018. [link]
  • S. Chowdhury, X. Xu, M. Tehranipoor, D. Forte, “Aging Resistant RO PUF with Increased Reliability in FPGA”,  International Conference on Reconfigurable Computing and FPGAs (ReConFig), December 2017. [pdf]
  • H. Shen, F. Rahman, B. Shakya, X. Xu, M. Tehranipoor, D. Forte, “Poly-Si Based Physical Unclonable Functions”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 25, No. 11, November 2017. [link]
  • M.T. Rahman, A. Hosey, Z. Guo, J. Carroll, D. Forte, M. Tehranipoor, “Systematic Correlation and Cell Neighborhood Analysis of SRAM-PUF for Robust and Unique Key Generation,” Journal of Hardware and Systems Security (HaSS), Vol. 1, No. 2, June 2017. [link]
  • T. Byrant, S. Chowdhury, D. Forte, M. Tehranipoor, N. Maghari, “A Stochastic All-Digital Weak Physically Unclonable Function for Analog/Mixed-Signal Applications”, Hardware-Oriented Security and Trust (HOST), May 2017. [pdf]
  • T. Bryant, S. Chowdhury, D. Forte, M. Tehranipoor, N. Maghari, “A Stochastic Approach to Analog Physical Unclonable Function,” IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Oct. 2016. [pdf]
  • H. Shen, F. Rahman, B. Shakya, M. Tehranipoor, D. Forte,”Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs)”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2016. [pdf]
  • M.T. Rahman, F. Rahman, D. Forte, M. Tehranipoor, “An Aging-Resistant RO-PUF for Reliable Key Generation,” IEEE Transactions on Emerging Topics in Computing (TETC). [link]
  • M. T. Rahman, D. Forte, F. Rahman, M. Tehranipoor, “A Pair Selection Algorithm for Robust RO-PUF Against Environmental Variations and Aging,” IEEE International Conference on Computer Design (ICCD), Oct. 2015. [pdf]
  • A. Mazady, M.T. Rahman, D. Forte, M. Anwar, “Memristor Nano-PUF A Security Primitive: Theory and Experiment,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS),    Vol. 5, No. 2, June 2015. [link]
  • A. Hosey, M.T. Rahman, K. Xiao, D. Forte, M. Tehranipoor, “Advanced Analysis of Cell Stability for Reliable SRAM PUF,” in IEEE Asian Test Symposium (ATS), 2014 . [pdf]
  • K. Xiao, M.T. Rahman, D. Forte, M. Su, Y. Huang, M.Tehranipoor, “Bit Selection Algorithm Suitable for High-Volume Production of SRAM-PUF,” in Hardware-Oriented Security and Trust (HOST), May 2014. [pdf]
  • M.T. Rahman, D. Forte, J. Fahrny, M. Tehranipoor, “ARO-PUF: An Aging-Resistant Ring Oscillator PUF Design,”Design, Automation, & Test in Europe (DATE), March 2014. [pdf]
  • D. Forte, A. Srivastava, “Improving the Quality of Delay-based PUFs via Optical Proximity Correction”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 32, No. 12, Dec. 2013 . [link]
  • D. Forte, A. Srivastava, “Manipulating Manufacturing Variations for Better Silicon-Based Physically Unclonable Functions”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), August  2012. [link]
  • D. Forte, A. Srivastava, “On Improving the Uniqueness of Silicon-Based Physically Unclonable Functions Via Optical Proximity Correction”, Design Automation Conference (DAC), June 2012. [DAC Best Paper Nomination] [link]

Design of True Random Number Generators (TRNGs)

  • T. Rahman, D. Forte, X. Wang, M. Tehranipoor, “Enhancing Noise Sensitivity of Embedded SRAMs for Robust True Random Number Generation in SoCs,” IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), Dec. 2016. [pdf]
  • M.T. Rahman, K. Xiao, D. Forte, X. Zhang, Z. Shi, M. Tehranipoor, “TI-TRNG: Technology Independent True Random Number Generator,” Design Automation Conference (DAC), June 2014. [link]